1. Field of the Invention
The present invention relates generally to package structures and fabrication methods thereof, and more particularly, to a package structure having an embedded semiconductor component and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are becoming lighter, thinner, shorter and smaller and developed towards high integration and multi-function. To meet the requirement of high integration and miniaturization for package structures, a BGA substrate design is introduced into packaging substrates and further the packaging type is developed from wire bonding type or flip chip type to a type of embedding such as an IC semiconductor chip in a packaging substrate so as to reduce the size of the overall semiconductor device and improve the electrical performance thereof.
On the other hand, single chip packaging types are being replaced by 3D and modular packaging types so as to obtain multi-chip SIP (system in package) packages.
FIG. 1A is a cross-sectional view of a conventional flip-chip coreless package structure. Referring to FIG. 1A, the package structure comprises a substrate 10, a solder mask layer 12 formed on the substrate 10, a chip 14 flip-chip mounted on the solder mask layer 12, and an underfill 16 filled between the chip 14 and the solder mask layer 12.
Therein, the substrate 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a. The substrate 10 has at least a dielectric layer 100, a wiring layer 101 formed on the dielectric layer 100 and a plurality of conductive vias 102 formed in the dielectric layer 100 and electrically connecting the wiring layer 102. Further, the wiring layer 102 comprises a plurality of first conductive pads 103 and a plurality of second conductive pads 104 exposed from the first surface 10a and the second surface 10b, respectively.
The solder mask layer 12 is formed on the first and second surfaces 10a, 10b of the substrate 10 and has a plurality of openings 120 for exposing the first and second conductive pads 103, 104, respectively, wherein the second conductive pads 104 are used for electrically connecting an external electronic device.
The chip 14 is flip-chip mounted on the solder mask layer 12 on the first surface 10a of the substrate 10. The chip 14 has an active surface 14a with a plurality of electrode pads 140 and an inactive surface 14b opposite to the active surface 14a, and the electrode pads 140 are electrically connected to the conductive pads 103 through solder bumps 15.
The underfill 16 is filled between the solder mask layer 12 and the active surface 14a of the chip 14 so as to encapsulate the solder bumps 15.
However, since the substrate 10 has an asymmetrical structure, it can easily deform due to an uneven force that causes the warpage of the overall structure, thus adversely affecting the electrical connection quality and reliability of the overall structure and reducing the product yield.
Further, since the package structure of FIG. 1A lacks the support of a core board, it results in an insufficient strength and easily causes the warpage of the overall structure. As such the electrical connection quality of the package structure as well as the underfill process are adversely affected.
FIG. 1B is a cross-sectional view of a conventional package structure having an embedded semiconductor component. Referring to FIG. 1B, the package structure comprises a core board 19 having opposite first and second surfaces 19a, 19b and a cavity 190 penetrating the first and second surfaces 19a, 19b; a chip 11 disposed in the cavity 190; a built-up structure 17 formed on the first and second surfaces 19a, 19b of the core board 19 and the chip 11; and a solder mask layer 18 formed on the built-up structure 17.
The chip 11 has an active surface 11a with a plurality of electrode pads 110 and an inactive surface 11b opposite to the active surface 11a. The chip 11 is fixed in the cavity 190 through an adhesive material 191.
The built-up structure 17 has at least a dielectric layer 170, a wiring layer 171 formed on the dielectric layer 170, and a plurality of conductive vias 172 formed in the dielectric layer 170 and electrically connecting the electrode pads 110 and the wiring layer 171.
The solder mask layer 18 has a plurality of openings 180 such that portions of the wiring layer 171 are exposed from the solder mask layer 18 to function as conductive pads for electrically connecting another electronic device.
The cavity 190 of the package structure of FIG. 1B is formed by using laser or a milling cutter. However, the laser process cannot be applied to a core board 19 with a thickness greater than 0.3 mm. Although there is no thickness limitation for a cutting process using a milling cutter, the process is time-consuming and has low accuracy.
Therefore, it is imperative provide a package structure and a fabrication method thereof so as to overcome the above-described drawbacks.